1. Field of the Invention
The present invention relates to a data output circuit, and more particularly, to a data output circuit by which, if an output voltage level is different from an operating voltage level, the difference is detected, and consequently the skew of an output data signal is controlled.
2. Description of the Related Art
As semiconductor devices evolve, they continue to consume a large amount of power while, at the same time, continue to demand high-speed operation. Accordingly, methods for reducing power consumption have been proposed, including the commonly used approach of lowering the operating voltage level.
Hence, in a single semiconductor device, circuits that interface with each other may use different voltage sources. In particular, a voltage source for operating the internal circuit of a semiconductor device may be different from a voltage source for an output driver circuit that outputs a data signal.
FIG. 1 is a circuit diagram of a conventional data output circuit that utilizes first and second operating voltage levels that are different. Referring to FIG. 1, a conventional data output circuit 100 includes a buffer logic unit 110, a pre-driver unit 120, and a main driver unit 130.
The buffer logic unit 110 buffers a data signal DATA and an inverted data signal DATA for a predetermined period of time in response to a clock signal CLK to obtain first and second data signals DATA1 and DATA2. To perform this operation, the buffer logic unit 110 includes transmission gates 111 and 113 and inverters I1, I2, I3, I4, and I5.
The buffer logic unit 110 can further include an NMOS transistor MN2 and resistors R1 and R2 for controlling skew of the second data signal DATA2 in response to a comparison voltage signal VCOM. Generation of the comparison voltage signal VCOM is described below with reference to FIG. 2.
Power for the buffer logic unit 110 is supplied according to the operating voltage level of.the internal circuit (not shown) of the data output circuit 100.
The pre-driver unit 120 converts the first and second data signals DATA1 and DATA2, which have an operating voltage level, into first and second driving signals DRV1 and DRV2, which have the output voltage level. The logic levels of the first and second data signals DATA1 and DATA2 are opposite to those of the first and second driving signals DRV1 and DRV2.
To perform the above operation, the pre-driver unit 120 includes NMOS transistors MN0 and MN1 and PMOS transistors MP0 and MP1, which are coupled between a first power supply voltage VDDQ and a first ground voltage VSSQ, which both have the output voltage level.
The main driver unit 130 outputs an output data signal DATAOUT in response to the first and second driving signals DRV1 and DRV2. To achieve this, the main driver unit 130 includes an NMOS transistor MN3 and a PMOS transistor MP3, which are coupled between a first power supply voltage VDDQ and a first ground voltage VSSQ, which both have the output voltage level.
The power for the buffer logic unit 110 of the conventional data output circuit 100 is supplied at a power supply voltage having the operating voltage level for operating the internal circuit (not shown) of the conventional data output circuit 100. Generally, the power supply voltage has a voltage level of 3.3V or 2.5V.
Both the pre-driver unit 120 and the main driver unit 130 have a first power supply voltage VDDQ and a first ground voltage VSSQ, which both have an output voltage level. The output voltage level is normally the same as an operating voltage level, but in recent trends the output voltage level is becoming lower than the operating voltage level when considering the need for high-speed operation and low power consumption in the output process.
In the conventional data output circuit 100, when the output voltage level used in the pre-driver unit 120 and the main driver unit 130 is different from the operating voltage level, the inclinations of the first and second driving signals DRV1 and DRV2 of the pre-driver unit 120 are changed, and consequently the output data signal DATAOUT is skewed.
In order to prevent skewing, the data output circuit 100 activates the comparison voltage signal VCOM and shortens the time required to transfer the second driving signal DRV2 to a high level by using a turn-on resistor of the NMOS transistor MN2 rather than the second resistor R2.
The comparison voltage signal VCOM may be automatically generated by detecting a change in the level of the first power supply voltage VDDQ with an output voltage level, or may be set through a mode register setting (MRS) process upon power-up of the circuit, or may be pre-programmed in a fuse-cutting procedure, for example.
FIG. 2 is a circuit diagram of a circuit for automatically generating the comparison voltage signal of FIG. 1. Referring to FIG. 2, an appropriate reference potential for a second power supply voltage VDD with an operating voltage level is generated using the ratio of resistances RA and RB. The reference potential is compared with the first power supply voltage VDDQ having the output voltage level in comparator 210.
If the level of the first power supply voltage VDDQ is equal to or less than a predetermined voltage level, a comparative voltage signal VCOM at an active, or high, level is generated at inverter 220.
However, the conventional method of FIG. 2 of automatically sensing a change in the first power supply voltage VDDQ has a problem in that the reference potential itself may be changed since the resistors RA and RB are sensitive to process change and the voltage level of the second power supply voltage VDD may vary, for example, by xc2x10.3V.
The method of FIG. 1 of changing the turn-on resistance of the NMOS transistor MN2 by activating the comparison voltage signal VCOM also has some problems in that the turn-on resistance of the NMOS transistor MN2 cannot be zero and can vary as a result of variation in the voltage level of the comparison voltage signal VCOM that is made depending on the voltage level of the second power supply voltage VDD.
In order to activate the output data signal DATAOUT of FIG. 1, the first driving signal DRV1 must have a low level, or the second driving signal DRV2 must have a high level.
In order to achieve this, the level of the first data signal DATA1 of FIG. 1 must be high so that a voltage Vgs between the gate and source of the NMOS transistor MN0 is VDD-VSSQ. Alternatively, the level of the second data signal DATA2 of FIG. 1 must be low so that a voltage Vgs between the gate and source of the PMOS transistor MP1 is VDDQ-VSS.
However, if the voltage level of the first power supply voltage VDDQ changes, the voltage Vgs between the gate and source of the NMOS transistor MN0 does not change, however, the voltage Vgs between the gate and source of the PMOS transistor MP1 changes according to the voltage level of the first power supply voltage VDDQ.
Consequently, when the level of the first power supply voltage VDDQ is low, the voltage Vgs between the gate and source of the PMOS transistor MP1 is reduced. Thus, the slope of the second driving signal DRV2 becomes more gradual, and, as a result, the output data signal DATAOUT becomes additionally skewed.
Accordingly, the present invention provides a data output circuit by which, in the case where an output voltage level is different from an operating voltage level, a variation in the output voltage level is detected, and consequently the skew of the output data signal is controlled.
According to a first aspect of the present invention, there is provided a data output circuit including first and second inversion units, first and second voltage compensation units, and a driver unit. The first inversion unit receives a first data signal of an operating voltage level and inverts the received first data signal to obtain a first inverted data signal. If a first power supply voltage of an output voltage level is different from a second power supply voltage of the operating voltage level by at least a predetermined voltage level, the first voltage compensation unit compensates for the voltage level of the first inverted data signal to obtain a first driving signal. The second inversion unit receives a second data signal with the operating voltage level and inverts the received second data signal to obtain a second inverted data signal. If the levels of the first and second power supply voltages are different by at least a predetermined voltage level, the second voltage compensation unit compensates for the voltage level of the second inverted data signal to obtain a second driving signal. The driver unit receives the first and second driving signals and outputs an output data signal with a logic level that is opposite to the logic levels of the first and second driving signals.
The first inversion unit forms an inverter by a first PMOS transistor and a first NMOS transistor being serially connected between the first power supply voltage and a first ground voltage of the output voltage level. The first data signal is applied to the gate of the first PMOS transistor and the gate of the first NMOS transistor.
The second inversion unit forms an inverter by a second PMOS transistor and a second NMOS transistor being serially connected between the first power supply voltage and the first ground voltage. The second data signal is applied to the gate of the second PMOS transistor and the gate of the second NMOS transistor.
The first voltage compensation unit includes first and second compensation PMOS transistors. The first compensation PMOS transistor has a source connected to the second power supply voltage and a gate subjected to the first power supply voltage. The second compensation PMOS transistor has a source connected to the drain of the first compensation PMOS transistor, a gate subjected to the first data signal, and a drain connected to a connection node between the first PMOS transistor and the first NMOS transistor.
The first voltage compensation unit compensates for the voltage level of the first inverted data signal if the first and second power supply voltages are different by at least a threshold voltage level of the first compensation PMOS transistor.
The second voltage compensation unit includes third and fourth compensation PMOS transistors. The third compensation PMOS transistor has a source connected to the second power supply voltage and a gate subjected to the first power supply voltage. The fourth compensation PMOS transistor has a source connected to the drain of the third compensation PMOS transistor, a gate subjected to the second data signal, and a drain connected to a connection node between the second PMOS transistor and the second NMOS transistor.
The second voltage compensation unit compensates for the voltage level of the second inverted data signal if the first and second power supply voltages are different by at least a threshold voltage level of the third compensation PMOS transistor.
The first and second data signals preferably have the same level.
The first voltage compensation unit includes first and second compensation PMOS transistors, first through N-th load PMOS transistors, and a first load NMOS transistor. The first compensation PMOS transistor has a source connected to the second power supply voltage and a gate subjected to a first drop voltage. The second compensation PMOS transistor has a source connected to the drain of the first compensation PMOS transistor, a gate subjected to the first data signal, and a drain is connected to a connection node between the first PMOS transistor and the first NMOS transistor. The first through N-th load PMOS transistors are serially connected to the first power supply voltage. The first load NMOS transistor is connected between the N-th load PMOS transistor and a second ground voltage, and has a drain which generates the first drop voltage and a gate and a source which are connected to each other.
The voltage compensation unit compensates for the voltage level of the first inverted data signal if the second power supply voltage and the first drop voltage are different by at least the threshold voltage level of the first compensation PMOS transistor. The level of the first drop voltage is determined according to the number of first through N-th load PMOS transistors.
The second voltage compensation unit includes third and fourth compensation PMOS transistors, (N+1)th through M-th load PMOS transistors, and a second load NMOS transistor. The third compensation PMOS transistor has a source connected to the second power supply voltage and a gate subjected to a second drop voltage. The fourth compensation PMOS transistor has a source connected to the drain of the third compensation PMOS transistor, a gate subjected to the second data signal, and a drain connected to a connection node between the second PMOS transistor and the second NMOS transistor. The (N+1)th through M-th load PMOS transistors are serially connected to the first power supply voltage. The second load NMOS transistor is connected between the M-th load PMOS transistor and a second ground voltage, and has a drain which generates the second drop voltage and a gate and a source which are connected to each other.
The second voltage compensation unit compensates for the voltage level of the second inverted data signal if the second power supply voltage and the second drop voltage are different by at least the threshold voltage level of the third compensation PMOS transistor. The level of the second drop voltage is determined according to the number of (N+1)th through M-th load PMOS transistors.
According to a second aspect of the present invention, there is provided a data output circuit including first and second inversion units, first and second voltage compensation units, and a driver unit. If an output voltage level of a first power supply voltage is equal to an operating voltage level of a second power supply voltage, the first inversion unit receives a first data signal of an operating voltage level and inverts the received first data signal to obtain a first inverted data signal. If the levels of the first and second power supply voltages are different by at least a voltage level, the first voltage compensation unit compensates for the voltage level of the first inverted data signal to obtain a first driving signal. If the levels of the first and second power supply voltages are the same, a second inversion unit receives a second data signal with an operating voltage level and inverts the received second data signal to obtain a second inverted data signal. If the levels of the first and second power supply voltages are different by at least a predetermined voltage level, a second voltage compensation unit compensates for the voltage level of the second inverted data signal to obtain a second driving signal. The driver unit receives the first and second driving signals and outputs an output data signal with a logic level that is opposite to the logic levels of the first and second driving signals.
The first inversion unit includes first and second inversion PMOS transistors, a first inversion NMOS transistor, and a first control voltage generation unit. The first inversion PMOS transistor has a source connected to the first power supply voltage and a gate subjected to a first control voltage. The second inversion PMOS transistor has a source connected to the drain of the first inversion PMOS transistor, a gate subjected to the first data signal, and a drain which generates the first inverted data signal. The first inversion NMOS transistor has a drain connected to the drain of the second inversion PMOS transistor, a gate subjected to the first data signal, and a source connected to a first ground voltage. If the levels of the first and second power supply voltages are the same, the first control voltage generation unit generates the first control voltage to have a first logic level. If the level of the first power supply voltage is less than that of the second power supply voltage by a predetermined voltage level, the first control voltage generation unit generates the first control voltage to have a second logic level.
The first control voltage generation unit includes a first control PMOS transistor, first through N-th load PMOS transistors, and a first control NMOS transistor. The first control PMOS transistor has a source connected to the second power supply voltage and a gate subjected to the first power supply voltage. The first through N-th load PMOS transistors are serially connected to the first control PMOS transistor. The first control NMOS transistor is connected between the N-th load PMOS transistor and a second ground voltage, and has a drain which generates the first control voltage and a gate and a source which are connected to each other.
The first voltage compensation unit includes first and second compensation PMOS transistors. The first compensation PMOS transistor has a source connected to the second power supply voltage and a gate subjected to the first power supply voltage. The second compensation PMOS transistor has a source connected to the drain of the first compensation PMOS transistor, a gate subjected to the first data signal, and a drain connected to a connection node between the second inversion PMOS transistor and the first inversion NMOS transistor.
The first voltage compensation unit compensates for the voltage level of the first inverted data signal if the first and second power supply voltages are different by at least a threshold voltage level of the first compensation PMOS transistor.
The second inversion unit includes third and third inversion PMOS transistors, a second inversion NMOS transistor, and a second control voltage generation unit. The third inversion PMOS transistor has a source connected to the first power supply voltage and a gate subjected to a second control voltage. The fourth inversion PMOS transistor has a source connected to the drain of the third inversion PMOS transistor, a gate subjected to the second data signal, and a drain which generates the second inverted data signal. The second inversion NMOS transistor has a drain connected to the drain of the fourth inversion PMOS transistor, a gate subjected to the second data signal, and a source connected to a first ground voltage. If the levels of the first and second power supply voltages are the same, the second control voltage generation unit generates the second control voltage to have a first logic level. If the level of the first power supply voltage is less than that of the second power supply voltage by a predetermined voltage level, the second control voltage generation unit generates the second control voltage to have a second logic level.
The second control voltage generation unit includes a second control PMOS transistor, (N+1)th through M load PMOS transistors, and a second control NMOS transistor. The second control PMOS transistor has a source connected to the second power supply voltage and a gate subjected to the first power supply voltage. The (N+1)th through M load PMOS transistors are serially connected to the second control PMOS transistor. The second control NMOS transistor is connected between the M-th load PMOS transistor and a second ground voltage, and has a drain which generates the second control voltage and a gate and a source which are connected to each other.
The second voltage compensation unit includes third and fourth compensation PMOS transistors. The third compensation PMOS transistor has a source connected to the second power supply voltage and a gate subjected to the first power supply voltage. The fourth compensation PMOS transistor has a source connected to the drain of the third compensation PMOS transistor, a gate subjected to the second data signal, and a drain connected to a connection node between the fourth inversion PMOS transistor and the second inversion NMOS transistor.
The second voltage compensation unit compensates for the voltage level of the second inverted data signal if the first and second power supply voltages are different by at least a threshold voltage level of the third compensation PMOS transistor.
The first and second data signals preferably have the same level.
According to a third aspect of the present invention, there is provided a data output circuit including first and second inversion units, first and second voltage compensation units, first and second control units, and a driver unit. If an output voltage level of a first power supply voltage is equal to an operating voltage level of a second power supply voltage, the first inversion unit receives a first data signal of an operating voltage level and inverts the received first data signal to obtain a first inverted data signal. If the levels of the first and second power supply voltages are different by at least a predetermined voltage level, the first voltage compensation unit compensates for the voltage level of the first inverted data signal to obtain a first driving signal. If the levels of the first and second power supply voltages are the same, the first control unit generates a first control signal for controlling the operation of the first voltage compensation unit. If the levels of the first and second power supply voltages are different by at least a predetermined voltage level, the first control unit generates a second control signal for controlling the operation of the first inversion unit. If the levels of the first and second power supply voltages are the same, the second inversion unit receives a second data signal with an operating voltage level and inverts the received second data signal to obtain a second inverted data signal. If the levels of the first and second power supply voltages are different by at least a predetermined voltage level, the second voltage compensation unit compensates for the voltage level of the second inverted data signal to obtain a second driving signal. If the levels of the first and second power supply voltages are the same, the second control unit generates a third control signal for controlling the operation of the second voltage compensation unit. If the levels of the first and second power supply voltages are different by at least a predetermined voltage level, the second control unit generates a fourth control signal for controlling the operation of the second inversion unit. The driver unit receives the first and second driving signals and outputs an output data signal with a logic level that is opposite to the logic levels of the first and second driving signals.
The first inversion unit includes first and second inversion PMOS transistors and a first inversion NMOS transistor. The first inversion PMOS transistor has a source connected to the first power supply voltage and a gate subjected to the second control signal. The second inversion PMOS transistor has a source connected to the drain of the first inversion PMOS transistor, a gate is subjected to the first data signal, and a drain which generates the first inverted data signal. The first inversion NMOS transistor has a drain connected to the drain of the second inversion PMOS transistor, a gate subjected to the first data signal, and a source connected to a first ground voltage.
The first control unit includes a first control PMOS transistor, a first control NMOS transistor, and first and second inverters. The first control PMOS transistor has a source connected to the second power supply voltage and a gate subjected to the first power supply voltage. The first control NMOS transistor has a drain connected to the drain of the first control PMOS transistor and a gate and a source which are connected to a second ground voltage. The first inverter is connected to a connection node between the first control PMOS transistor and the first control NMOS transistor, and generates the first control signal. The second inverter is connected to the first inverter and generates the second control signal.
The first voltage compensation unit includes first and second compensation PMOS transistors. The first compensation PMOS transistor has a source connected to the second power supply voltage and a gate subjected to the first control signal. The second compensation PMOS transistor has a source connected to the drain of the first compensation PMOS transistor, a gate subjected to the first data signal, and a drain connected to a connection node between the second inversion PMOS transistor and the first inversion NMOS transistor.
The second inversion unit includes third and fourth inversion PMOS transistors and a second inversion NMOS transistor. The third inversion PMOS transistor has a source connected to the first power supply voltage and a gate subjected to a fourth control signal. The fourth inversion PMOS transistor has a source connected to the drain of the third inversion PMOS transistor, a gate subjected to the second data signal, and a drain which generates the second inverted data signal. The second inversion NMOS transistor has a drain connected to the drain of the fourth inversion PMOS transistor, a gate subjected to the second data signal, and a source connected to a first ground voltage.
The second control unit includes a second control PMOS transistor, a second control NMOS transistor, and third and fourth inverters. The second control PMOS transistor has a source connected to the second power supply voltage and a gate subjected to the first power supply voltage. The second control NMOS transistor has a drain connected to the drain of the second control PMOS transistor and a gate and a source which are connected to a second ground voltage. The third inverter is connected to a connection node between the second control PMOS transistor and the second control NMOS transistor, and generates the third control signal. The fourth inverter is connected to the third inverter and generates the fourth control signal.
The second voltage compensation unit includes third and fourth compensation PMOS transistors. The third compensation PMOS transistor has a source connected to the second power supply voltage and a gate subjected to the third control signal. The fourth compensation PMOS transistor has a source connected to the drain of the first compensation PMOS transistor, a gate subjected to the second data signal, and a drain connected to a connection node between the fourth inversion PMOS transistor and the second inversion NMOS transistor.
The first and second data signals preferably have the same level.